The performance of non-volatile memory cells typically degrades over the device's lifetime due to various impairments. As a result, storage reliability of the memory cells may degrade below an acceptable level.
Methods for estimating the performance of non-volatile memory cells are known in the art. For example, U.S. Pat. No. 9,431,130 describes a memory controller that includes a decoding unit. The decoding unit calculates a syndrome weight in an LDPC code using a code word read out from a non-volatile memory. The memory controller instructs the non-volatile memory to perform readout using first and second read-out voltages, and determines the first read-out voltage as the optimal read-out voltage in the case where a first syndrome weight based on a read-out result at the first read-out voltage is equal to or less than a second syndrome weight based on a read-out result at the second read-out voltage.
U.S. Pat. No. 9,563,502 describes methods and apparatus for read retry operations with read reference voltages ranked for different page populations of a memory. One method comprises obtaining a plurality of rankings of a plurality of read reference voltages for a plurality of page populations, wherein the rankings are based on a predefined performance metric; and reading a code word from the memory a plurality of times, wherein each of the read operations uses a different one of the plurality of read reference voltages selected based on the rankings. The performance metric comprises, for example, a bit error rate, a bit polarity disparity, a substantially minimal syndrome weight and/or measures of an average system latency or a tail latency.